1. Field of the Invention
This invention relates generally to semiconductor device, and, more particularly, to a protective layer for use in packaging a semiconductor device.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconductor substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnect structures. Many modem integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnect structures must be made in multiple layers to conserve plot space on the semiconductor substrate.
Commonly, dielectric layers, such as silicon oxide or silicon nitride, are formed between various layers during the manufacture of the semiconductor device. In cases where copper is used to form the conductive interconnect structures in the semiconductor device, the dielectric layer may act as a protective layer to prevent diffusion of the copper and as an antireflective coating for subsequent photolithography steps. Passivation layers, also formed of silicon nitride, for example, may be formed above the topmost layer of the semiconductor device. Typically, such a passivation layer acts as a barrier to contaminants that may cause the underlying semiconductor device to operate in an undesirable manner or to fail.
FIG. 1A shows an exemplary prior art semiconductor device 100. The semiconductor device 100 includes at least one, and typically several, device layer(s) 105, which may contain transistors, interconnect structures, and the like, as discussed above. One or more metal structures 110 may be formed above the device layer 105. For example, the metal structures 110 may be electrical contacts and/or interconnects used to provide conductive connections to the integrated circuits in the device layer(s) 105. The metal structures 110 may also be pads, gates, or the like. The device layer(s) 105 may be formed above a semiconductor substrate (not shown) or above another device layer (not shown).
One or more passivation layers 120, 125, 130 may be formed above the metal structures 110 and the device layer 105. In the illustrated embodiment, the passivation layers 120, 125, 130 are a tetraethyl orthosilicate (TEOS) layer 120, a nitride passivation layer 125, and a polyimide layer 130. However, it will be appreciated that, in alternative embodiments, fewer passivation layers 120, 125, 130 may be formed above the metal structures 110. For example, the polyimide layer 130 may not be included. The passivation layers 120, 125, 130 may be formed by a variety of processes known to those of ordinary skill in the art, including chemical vapor deposition, plasma-enhanced chemical vapor deposition, spin-on processes, thermal growth, and the like.
After the semiconductor device 100 has been formed, typically in a wafer containing many such semiconductor devices 100, it may be installed in a package suitable for use in combination with other components, in forming a system, for example. During the packaging process, the passivation layers 120, 125, 130 may be damaged and the reliability of the semiconductor device 100 may be compromised. FIG. 1B shows an exemplary packaged semiconductor device 100. To package the semiconductor device 100, a package substrate 150 may be deployed above the passivation layers 120, 125, 130, in a manner well known to those of ordinary skill in the art. A mold compound 140, such as an epoxy-based compound, may then be injected into the package body in the space between the package substrate 150 and the passivation layers 120, 125, 130. Those of ordinary skill in the art will be well versed in injection processes used for this purpose.
During the packaging process, filler particles 160 in the mold compound 140 can become trapped between the semiconductor device 100 and the substrate 150. For example, the filler particles 160 may be SiO2. As the mold compound 140 is forced into the space between the substrate 150 and the semiconductor device 100, the filler particles 160 may be pushed into the passivation layers 120, 125, 130. For example, a force, indicated by the arrow 155, may be applied to position the substrate 150 above the mold compound 140. In response to the force 155 applied to the substrate 150, the filler particles 160 may exert a force, indicated by the arrow 170, on the passivation layers 120, 125, 130.
The force 170 may result in stress fractures in one or more of the passivation layers 120, 125, 130, causing one or more of the passivation layers 120, 125, 130 to function in an undesirable manner or to fail. For example, the filler particles 160 may cause stress defect failures 175 in the nitride layer 125 and/or the TEOS layer 120, thus adversely affecting the metal structures 110 and/or the device layer 105. The stress defect failures 175 may also create points of failure in the metal structures 110 and/or the various structures that may be formed in the device layer 105 and, consequently, the stress defect failures 175 may cause the semiconductor device 100 to operate in an undesirable manner or to fail altogether.
The present invention is intended to overcome, or at least reduce the effects of, one or more of the above problems.